This invention is generally related to the control of power consumption in data processing circuitry, and more particularly to controlling power consumption in clocked, high speed logic circuits that feature synchronous and precisely timed accesses.
Modem, complex, high speed logic circuits, such as a processor and memory combination in a computer system, can consume a significant amount of power. In certain cases, such as the processor becoming too hot or, in portable systems, a battery being depleted too quickly, it is desirable to reduce the power consumption yet still allow data processing to continue albeit at a reduced throughput.
A technique known as stop clock throttling periodically shuts off an on-chip clock fed to certain logic units in the processor chip. This is done by qualifying or switching the on-chip clock signal in accordance with a periodic stop clock signal. Since the logic units operate only in the presence of the on-chip clock, the logic units are essentially disabled, and processing is halted, during the interval in which the stop clock signal is asserted. Processing resumes when the stop clock is deasserted. By appropriately selecting the duty cycle of the stop clock signal, power consumption can be controlled while still allowing processing to continue at reduced throughput.
A problem with conventional stop clock throttling, however, occurs when the frequency of the stop clock signal is in the relatively broad human audible range of a few tens of hertz to several thousands of hertz. The stop clock signal causes periodic surges in the power consumption of the computer system. This in turn leads to power components such as inductors in the computer system to physically oscillate in accordance with the stop clock signal and thereby emit a constant but annoying audible tone.